This website uses cookies primarily for visitor analytics. Certain pages will ask you to fill in contact details to receive additional information. On these pages you have the option of having the site log your details for future visits. Indicating you want the site to remember your details will place a cookie on your device. To view our full cookie policy, please click here. You can also view it at any time by going to our Contact Us page.

Improved FPGA design productivity for LabVIEW

07 August 2012

National Instruments has introduced the LabVIEW FPGA (field programmable gate array) IP Builder add-on, which uses Xilinx Vivado high-level synthesis technology to simplify high-performance field-programmable gate array (FPGA) algorithm design.

The add-on is designed to enhance productivity by reducing the need for manual optimisation of high-performance algorithms. Instead, users specify functional behaviour along with design constraints and the software automatically generates a hardware implementation to meet requirements.

The new add-on tightly integrates with LabVIEW and the LabVIEW DSP Design Module, which helps researchers and system designers in the RF and telecommunications space to quickly create communication links and multirate digital signal processing (DSP) algorithms on FPGAs.
Product features include increased FPGA design abstraction for enhanced productivity, improved algorithm performance and resource utilisation, separation of code and design constraints facilitates IP reuse, and seamless deployment to the company’s FPGA-based devices and integration with I/O.

A whitepaper from National Instruments offers advice on how to get better system performance and resource utlisation through LabVIEW FPGA IP Builder.

To download the whitepaper go to:

Contact Details and Archive...

Print this page | E-mail this page